Semiconductor devices are widely used in various types of electronic products, consumer products, printed circuit cards, and the like. In an integrated circuit, a number of active semiconductor devices are formed on a chip ("die") of silicon and the chip circuit is interconnected to package leads to form a complete circuit. The size and cost of the semiconductor devices are important features in many of these applications. Any reduction in the cost of producing the package or reduction in the size of the package can provide a significant commercial advantage.
The integrated circuit chips are mounted on substrates which physically support them and provide electrical interconnections with other circuitry. The interconnections between the chip itself and the supporting substrate is known as "first level" assembly or chip interconnection, while the interconnection between the substrate and other circuitry is referred to as "second level" interconnection.
One type of first level interconnection commonly used is the tape automated bonding (TAB) technique. Utilizing this technique, a polymer tape is provided with thin layers of metallic material forming conductors on one surface. These conductors are arranged generally in a ring-like pattern and extend generally radially, towards and away from the center of the ring-like pattern. A semiconductor chip is placed on the tape face down, with the contacts of the chip aligning with the conductors on the tape. The contacts on the chip are electrically bonded to the conductors on the tape. Due to the flexibility of the tape, the structure is not subject to stresses on the connections caused by differing coefficients of thermal expansion. However, because the leads utilized in tape automated bonding extend radially outward in a fan out pattern from the chip, the entire assembly is necessarily much larger than the chip itself, requiring additional space for mounting.
Another type of first level interconnection commonly used is the "flip-chip" bonding technique. Utilizing this technique, the bond pads on the top side of semiconductor chip or die are provided with conductive solder balls. The number and arrangement of the conductive solder balls depends on the circuit requirements, including input/output (I/O), power and ground connections. Advanced chips capable of performing numerous functions may require hundreds or even thousands of I/O connections on a single chip.
The substrate is provided with a series of metal traces on its top surface, each of which terminates with a contact pad. The contact pads are arranged in an array corresponding to the array of solder balls on the top of the chip. The chip is then inverted so that its top side faces toward the top surface of the substrate and its solder balls are in direct physical contact with the corresponding contact pads of the substrate. The solder balls are liquefied by applying heat and pressure through the chip, thereby establishing a direct metallurgical bond between the chip's bond pads and the substrate's contact pads.
The use of the flip-chip technique provided a compact assembly, since the area of the substrate occupied by the contact pads is approximately the same size as the chip itself. Additionally, by utilizing substantially the entire top side of the chip for the bond pads, flip-chip bonding is well suited to use the chips having large numbers of I/O contacts. However, one disadvantage of the flip-chip technique is the substantial stress placed on the first level interconnection structures connecting a chip to a substrate caused by thermal cycling as temperatures within the device fluctuate during operation.
As electrical power is dissipated within the chip, heat is generated which causes the temperature of the chip and substrate to fluctuate as the device is turned on and off. This thermal cycling causes the chip and substrate to expand and contract in accordance with their respective coefficients of thermal expansion (CTE). The coefficient of thermal expansion typically varies for materials of differing composition; thus, the chip and substrate, normally formed of different materials, will expand and contract at different rates and by different amounts. The expansion and contraction can cause the bond pads on the chip to move relative to the contact pads on the substrate. This relative movement places the electrical interconnections under mechanical stress. The repeated application of this stress can result in the breaking of the electrical interconnections, thereby causing the device to malfunction.
Even if the chip and substrate are formed of like materials having similar coefficients of thermal expansion, thermal cycling stresses may still occur because the temperature of the chip may increase more rapidly than the temperature of the substrate when power is first applied to the chip.
Thus, due to the mismatch between the coefficients of thermal expansion of the chip and of the substrate or the disparate heating of the chip and substrate, the temperature range within which the packaged integrated circuit can be used without the reliability of the circuit being impaired due to differential thermal expansion is quite small.
The size of the chip and substrate assembly are also important features. It is frequently desired that several chips be mounted on a single substrate, since there is a need to interconnect a large number of integrated circuits together to provide a complete system.
For example, an exemplary computer system includes one or more processing elements (e.g. microprocessors), a plurality of memory circuits, controller circuits, etc. These circuits are typically packaged in carriers, which are typically interconnected on printed circuit boards. The space required for the package material and the space required for the interconnection wiring between the integrated circuit occupies a substantial portion of the printed circuit board space, which influences the size of the overall electronic device. Furthermore, the required distance between each chip and other chips is determined by the size of each assembly. Delays in propagation of electric signals between the chips are directly related to these distances. Propagation delays limit the speed of the operation of the device. Thus, smaller distances between the chips corresponds to smaller propagation delays and permits taster operation of the device.
The present invention has been designed to address the needs of the electronics industry and to overcome some of the limitations associated with the compact packaging of integrated circuits.